Field of the Invention
The present invention relates to an interface circuit that allows a digital signal to be supplied or received between two circuit blocks.
Description of the Related Art
In recent years, there has been an increased demand for a technique for providing a semiconductor integrated circuit or a circuit system (which will collectively be referred to as a “semiconductor integrated circuit” hereafter) with reduced power consumption. In order to meet such a demand, the semiconductor integrated circuit is configured as multiple circuit blocks, and is configured such that each circuit block operates with a different optimum voltage amplitude or otherwise with a different power supply voltage.
FIG. 1 is a block diagram showing a semiconductor integrated circuit including multiple circuit blocks. A semiconductor integrated circuit 2r includes a first circuit 4, a second circuit 6, and an interface circuit 10r. The first circuit 4 is connected to a power supply rail configured to supply a first power supply voltage VDD1 and a ground voltage VSS. The internal digital signal of the first circuit 4 swings in a binary manner between the first power supply voltage VDD1 as high level and the ground voltage VSS as low level. The second circuit 6 is connected to a power supply rail configured to supply a second power supply voltage VDD2 and the ground voltage VSS. The internal digital signal in the second circuit 6 swings in a binary manner between the second power supply voltage VDD2 as high level and the ground voltage VSS as low level.
Description will be made below regarding an arrangement in which VDD1<VDD2. The interface circuit 10r is interposed between the first circuit 4 and the second circuit 6. The interface circuit 10r receives an input signal IN that transits between VSS and VDD1, converts the input signal IN into an output signal OUT that full-scale swings between VSS and VDD2, and outputs the output signal OUT thus converted to the second circuit 6 configured as a downstream stage.
As a result obtained by investigating the current consumption (power consumption) required for the overall operation of the semiconductor integrated circuit 2r, the following problem has been found.
Description will be made regarding an arrangement in which the second circuit 6 is configured as a digital circuit according to a CMOS (Complementary Metal Oxide Semiconductor) architecture. The current consumption of the digital circuit is represented by the sum total of (i) loss due to the charge/discharge current used to charge/discharge a parasitic capacitor that occurs due to a transistor, wiring, or the like, (ii) loss due to a through current that flows through a CMOS inverter configured as an internal component, (iii) loss due to leak current, etc. The ratio of such current loss components varies according to the circuit scale, the circuit operating condition, and the like. The through current flows when the upper-side PMOS transistor and the lower-side NMOS transistor that form the CMOS inverter turn on at the same time. Specifically, the through current flows when the input signal of the CMOS inverter is set to an intermediate voltage level between the high-level voltage and the low-level voltage, i.e., when transition occurs in the input signal. In a digital circuit that operates together with an upstream circuit that operates with low power consumption, the signal received from the upstream-stage circuit transits at a low speed. Thus, in particular, such an arrangement leads to a problem of current loss due to a through current that occurs when a signal having such a low transition speed propagates through the digital circuit.
With the semiconductor integrated circuit 2r shown in FIG. 1, in order to reduce the power consumption of the second circuit 6, the through current that occurs in the CMOS inverter configured as a component of the semiconductor integrated circuit 2 may preferably be reduced. In order to reduce the through current, the input signal may preferably be configured to have an increased transition speed (through rate).
FIGS. 2A and 2B are circuit diagrams each showing an interface circuit 10r investigated by the present inventor. It should be noted that the interface circuit 10r cannot be recognized as a known technique. The interface circuit 10r shown in FIG. 2A includes a voltage comparator 200. The voltage comparator 200 requires the supply of a stationary current Ic regardless of whether or not there is transition of the signal, leading to large power consumption. Furthermore, in order to raise the transition speed of the output signal OUT, there is a need to increase the amount of current Ic. Thus, such an arrangement is unsuitable for such a usage having a strong demand for reducing power consumption.
The interface circuit 10r shown in FIG. 2B is configured as a level shifter 202 including two cross-coupled CMOS inverters 204 and 206. During a period in which there is no level transition in the signal, the level shifter 202 requires no current consumption. However, in a case in which the input signal INP/INN has a low transition speed, a through current flows in a transition period. This leads to difficulty in providing reduced power consumption.